Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of a central processing unit (CPU). Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards. Computers provided with DMA channels can typically transfer data to and from devices with much less CPU overhead than computers without a DMA channel.
DMA is commonly used to allow devices to transfer data without exposing the CPU to a heavy load. If the CPU had to copy each piece of data from the source to the destination, this would be typically slower than copying normal blocks of memory, since access to I/O devices over a peripheral bus is generally slower than normal system RAM. During this time the CPU would be unavailable for other tasks involving CPU bus access, although it could continue doing any work which did not require bus access.
A DMA transfer essentially copies a block of memory from one device to another. While the CPU initiates the transfer, it does not execute it. The transfer is usually performed by a DMA controller which is typically part of a motherboard chipset. A typical usage of DMA is copying a block of memory from system RAM to or from a buffer on the device, wherein the operation does not need much capacity of the processor, which as a result can be scheduled to perform other tasks. DMA is therefore essential to high performance embedded systems.
The DMA controller generally transfers data from a data source location to a data destination location. In some applications, DMA transfers are used in safety critical systems, wherein it is important that the DMA transfers perform the correct transfer operation. DMA operations may be particularly difficult to check as the autonomous nature of the process requires substantial supervision.
In particular, when a DMA is used to automatically unload data from an autonomous peripheral unit, such as serial interface, Analogue to Digital Converter (ADC), or input capture system, in a periodic way, it is often configured to move data from the peripheral unit to one or more memory buffers. The data that appears in the memory buffer is typically used by the control system for real-time control of the system actuators and communication interfaces. The data therefore has a temporal aspect, as the system should only be using current data that has just been transferred, rather than historical data. It is important to know that the data buffer has been refreshed since last time the data was used. Therefore, the CPU has to check the operation of the DMA transfers in real time, which requires a low latency service that is CPU intensive.
Typically, a known DMA peripheral performs data transactions within an embedded system which also comprises a host CPU. The CPU is responsible for supervising the correct operation of the DMA. A sequence of linked DMA transactions is correctly ordered by configuring the DMA and Interrupt Router to trigger the start of a new DMA transaction on completion of the preceding transaction in the sequence. A sequence of linked DMA transactions is usually ordered by either of the following methods:                Configuring the DMA controller and interrupt router, such that the completion of an on-going DMA transaction initiates the start of the next DMA transaction via a hardware trigger.        The CPU intervenes between DMA transactions and initiates the start of the next DMA transaction via a software trigger on receiving a DMA traffic management semaphore that the preceding DMA transaction has completed.        
US 2009/0271536 discloses a DMA controller that conditionally executes I/O descriptors, wherein a linked list item contains a checksum computed on the descriptor fields. When the linked list item is fetched, the checksum is computed on the descriptor. If both checksums are equal, the linked list item is considered valid and the descriptor is executed. At the end of a DMA I/O, the next descriptor in the linked list is fetched. When the checksum fails, the descriptor is corrupted and the channel is stopped and an error is reported to the operating system.
These known approaches involve the following disadvantages:                The verification of the temporal sequence of DMA data moves requires intervention by the CPU to confirm the sequencing of events while a sequence of DMA transactions is in progress.        Post-processing of the DMA state does not guarantee correct operation.        Post-processing of the destination data that has been moved is CPU intensive.        
The present disclosure faces the challenge to provide solutions to the above mentioned problems.